Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PH…
- Verification IP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PH…
AMBA® ACE and CHI coherent interconnect technologies enable an entirely new class of high-performance datacenter applications in …
Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CX…
The AXI Bridge for PCIe IP core is the IP solution with a mix of multiple industry standard memory mapped AXI Interfaces.The AXI …
AXI Bridge with DMA for PCIe IP Core
The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a mix of multiple industry standard AXI Interfaces.
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs).
The K-best decoder is part of the MIMO decoder.
ISDB-S3-LDPC-BCH Decoder
The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz It supports adjustable…
Edge-friendly LLM and CNN AI Inference processing Edge devices are increasingly equipped with AI processing capabilities that enh…
Mobile-Centric LLM and CNN AI Inference processing Consumers are excited about the latest AI features in smartphones.
High Performance Scalability across Complex Models Cloud-based AI inference is the backbone of retail, e-commerce, healthcare, in…
Whether deployed in-cabin for driver distraction or in the driver assistance system (ADAS) stack for object recognition and point…
Arasan provides the xHCI (eXtensible Host Controller Interface) driver for the USB 3.0 Host stack that makes it possible to commu…
USB 2.0 OTG Dual Role Device (DRD) Controller
The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev.
SD 3.0/SDIO 3.0/eMMC 4.51 Host Controller Software Stack
This is a production-ready software stack for Arasan’s SD 3.0/ SDIO 3.0/ eMMC 4.51 Host Controller IP that is used to connect to …
eMMC 4.51 Device Controller IP
eMMC 4.51 is the latest specification released by JEDEC and is designed to meet the requirements for secure yet flexible program …
SD 4.1 Hardware Validation Platform
The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile …
MIPI SoundWire Slave Controller 1.2
MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphone…