Gen 4 2D (vector graphics) GPU IP
GV380S/GV380T comes with a significant enhancement of rendering performance.
- GPU
- Available
- OpenVG1.1
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Gen 4 2D (vector graphics) GPU IP
GV380S/GV380T comes with a significant enhancement of rendering performance.
The MGNSS IP (GNSS IP) is a silicon proven, AHB compliant, all-in view, Multi-constellation and Multi-frequency GNSS baseband IP …
Bitmap 2.5D Graphics Accelerator
The logiBMP is 2.5D graphics accelerator from Xylon logicBRICKS IP library, optimized for Xilinx FPGAs and designed to speed up g…
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
Band-gap Reference in GF N65 LP. Multiple voltages referenced to internal and external resistors.
The PMCC_REFS IP block combines two modules of GM current references and one module of BG (band-gap) current reference.
Color Camera Sensor Bayer Decoder
Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern.
Lancero Scatter-Gather DMA Engine for PCI Express
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI …
VISENGI's JPEG Decoder IP core has been developed to be a standards compliant M-JPEG Hardware Decoder.
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using c…
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU,…
NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
ntAES8 core implements NIST FIPS-197 Encryption Standard.
The VK-402 searches only within a fixed number of lattice points, where the number of considered lattice points decreases as we d…
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
This implementation of the AES-CCM algorithm implements the full NIST draft SP800-38C specification.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
High-performance implementation of Z80/Z180 instruction set
Two clock cycle machine cycle implementation of the Z80/Z180 instruction set.
Smallest, Lowest Power ARM Multicore Applications Processor
The Arm® Cortex®-A5 processor is the smallest, lowest power Arm multi-core processor capable of delivering the internet to the wi…
25 Gb/s AES-ECB 128/192/256 Crypto Cores
Concurrent EDA AES cores implement the 128-bit block size NIST FIPS AES Algorithm.