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Vendor:
Systemyde International Corp.
Category:
CPU
High-performance implementation of Z80/Z180 instruction set
Two clock cycle machine cycle implementation of the Z80/Z180 instruction set.
Overview
Two clock cycle machine cycle implementation of the Z80/Z180 instruction set. Optimized for ASIC or FPGA implementations.
This machine structure is derived from that used in the Rabbit
Semiconductor microprocessors. Performance for those
designs (which are more complex) is 200MHz in 90nm, or
100MIPS peak.
Key features
- Full Z80/Z180 instruction set. Separate memory and I/O buses,
- optimized for direct connection to standard ASIC or FPGA
- memories and industry-standard peripheral functions. Separate
- interrupt vector bus for use with an optionaql external interrupt
- controller.
- Optional full test suite.
- Optional full internal design documentation.
Benefits
- Full Z80/Z180 code compatibility.
- Average 33% clock cycle performance improvement over the
- standard Z180 timing. Average 50% clock cycle performance
- improvement over the standard Z80 timing.
- Uniform machine cycle timing makes interface design simple.
- Dedicated buses also simplify interface design.
What’s Included?
- Verilog source code.
- Optional test suite.
- Optional internal design documentation.
Specifications
Identity
Part Number
Y90
Vendor
Systemyde International Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about CPU IP cores
What is High-performance implementation of Z80/Z180 instruction set?
High-performance implementation of Z80/Z180 instruction set is a CPU IP core from Systemyde International Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.