Vendor: VISENGI Category: Video Processing

M-JPEG Decoder

VISENGI's JPEG Decoder IP core has been developed to be a standards compliant M-JPEG Hardware Decoder.

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Overview

VISENGI's JPEG Decoder IP core has been developed to be a complete standards compliant M-JPEG Hardware Decoder.

Key features

  • Baseline DCT decoder according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard
  • Seamless Motion JPEG (MJPEG) decoding
  • Dual pixel output for top speed (4 pixels decoded every 3 cycles)
  • Industry standard AXI interfaces (AXI and AXI4-stream for row-wise output)
  • Plug and Play IP blocks for Xilinx Vivado and Altera Quartus Qsys
  • No need for external CPU or memory.
  • Unlimited image size (specification up to 64K x64K)
  • Maximum number of Huffman and Quantization tables allowed by specification (four each)
  • Allows RST (restart intervals) and DNL (for multi-scan images) markers
  • Selectable YCbCr and/or RGB output
  • Throughput: up to 4 pixels output every 3 clock cycles

Benefits

  • VISENGI's JPEG Decoder features a dual pixel component pipeline, allowing for greater decoding speeds. And what is more important, a highly optimized Huffman decoder has been designed and fine tuned into the system.
  • These two features coupled make our JPEG Decoder unique in guaranteeing decoding speed even for the highest quality images (worst compression ratios), while other decoders can only sustain their throughputs at lower qualities and just advertise their maximum speed.

What’s Included?

  • Technical support
  • Documentation and design examples
  • Altera and Xilinx IP blocks
  • Instantation Templates

Specifications

Identity

Part Number
JPEG_Decoder
Vendor
VISENGI
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VISENGI
HQ: Spain
Contact VISENGI

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is M-JPEG Decoder?

M-JPEG Decoder is a Video Processing IP core from VISENGI listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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