The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and…
- SPI / QSPI XSPI
- In Production
- Immediate
- Yes
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and…
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory.
LIN 2.2, 2.1 and 1.3 Protocol Controller IP
The LIN is a soft core of the Local Interconnect Network (LIN).
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol.
CAN 2.0 & CAN FD Bus Controller IP
The CAN is a standalone controller for the Controller Area Network (CAN), which is commonly used in automotive and industrial app…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification.
HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification.
HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification.
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55LP
HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification.
HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' produ…
JPEG Encoder 4K(YUV422) 96fps@200MHz. (8Sample/clk)
The KJN-7ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec 4K(YUV422) 96fps@200MHz, (8Sample/clk)
The KJN-7 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder 4K(YUV422) 48fps@200MHz. (4Sample/clk)
The KJN-6ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec 4K(YUV422) 48fps@200MHz. (4Sample/clk)
The KJN-6 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 48fps@100MHz. (2Sample/clk)
The KJN-4 conform to the JPEG baseline format for compressing/decompressing still images.
JPEG Encoder Full HD(YUV422) 24fps@100MHz. (1Sample/clk)
The KJN-1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 24fps@100MHz.(1sample/clk)
The KJN-1+ conform to the JPEG baseline format for compressing/decompressing still images.
The LCD01G is a fully compatible GEO Mobile Radio (GMR-1) LDPC error control decoder.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.