The CC-WDT-AXI is a synthesisable Verilog model of a watchdog timer controller.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The CC-WDT-AXI is a synthesisable Verilog model of a watchdog timer controller.
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller.
Configurable System Tick Counter
The CC-SYSTICK-AXI is a synthesisable Verilog model of a system tick timer counter controller.
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller.
The CC-TIMER-AXI is a synthesisable Verilog model of a timer counter controller.
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller.
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller.
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller.
UART Serial Interface Controller
The CC-UART-AXI is a synthesisable Verilog model of a UART serial interface controller.
UART Serial Interface Controller
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller.
IEEE 802.15.4- 2011 - MAC and PHY
LTIMindtree IEEE 802.15.4 MAC and PHY semiconductor Intellectual Property (IP) is based on IEEE 802.15.4 specification.
Multi-protocol time synchronization IP
Provides sub-microsecond time synchronization, ensuring maximum flexibility for every scenario
IRIG 200-04 compliant time synchronization slave / time receiver for FPGA
IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices.
PTP ordinary (master / time transmitter & slave / time receiver) clock
Provides nanosecond level clock synchronized to network PTP time transmitter.
10M/100M/1G Managed Redundant Switch IP Core
HSR/PRP redundancy + Legacy ethernet ports