OFDM - Orthogonal Frequency Division Multiplexing
OFDM - Orthogonal Frequency Division Multiplexing
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OFDM - Orthogonal Frequency Division Multiplexing
OFDM - Orthogonal Frequency Division Multiplexing
40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
The TRV303TSM40LP IP is a 1.1V low-power, low-silicon-area and high-performance 6.0GHz-to-9.4GHz Fractional-N RF PLL implemented …
Bluetooth Connectivity Platform
The Ceva-Waves Bluetooth platform comprises a comprehensive set of hardware IP, software modules, and radios from Ceva and third-…
IEEE 802.11n/ac/ax (WiFi) LDPC Decoder and Encoder
The WiFi family of standards (IEEE 802.11) is used for Wireless Local Area Networks (WLANs).
eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…
GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital IP
This Ultra Low Power GNSS Multi-Constellation Digital IP is extracted from a production chipset supporting all the major constell…
This implementation of the AES-CCM algorithm implements the full NIST draft SP800-38C specification.
Dual band WiFi N/G/B/A Digital Baseband IP
Extracted from high volume production chip shipped in Tier 1 handsets, the 802.11 A/B/G/N Baseband/MAC wireless solution operatin…
802.11 BGN Low Power WIFI RF SoC
The Silicon chip supports 802.11bgn, 20Mhz/40Mhz standard.It supports PWM up to 6 channel, Co-existance interface to BLE / Zigbee…
10-bit, 2 GSPS SAR ADC - ST 28 nm
The A10B2G is a ultra low-power, high- speed analog to digital converter (ADC) intellectual property (IP) design block.
6-bit, 5 GSPS Flash ADC - STMicroelectronics 28nm
The A6B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.
802.11ax PHY Layer C Floating-Point Code IP for the STA mode
This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode.
The K-best decoder is part of the MIMO decoder.
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
10-bit, 500 MSPS SAR ADC - STMicroelectronics 28nm
The A10B500M is an ultra-low-power and high-speed analog to digital converter (ADC) intellectual property (IP) design block.
The K-best decoder is part of the MIMO decoder.
12-bit 4-channel 20 to 100 MSPS ADC
Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circui…