Secure RoT Core for Data Centers
Secure RoT with Post-Quantum Cryptography Datacenter-class SoCs such as CPUs, GPUs, DPUs, and NVMe controllers require a trusted …
- Root Of Trust
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Secure RoT Core for Data Centers
Secure RoT with Post-Quantum Cryptography Datacenter-class SoCs such as CPUs, GPUs, DPUs, and NVMe controllers require a trusted …
The Polyphase Video Scaler is a high performance, high quality, video scaler IP core capable of scaling up or down the input vide…
TCP/UDP/IP Network Protocol Accelerator Platform
Accelerate Network Protocols with FPGA TCP/UDP/IP Stack The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with M…
Data protection from safeguarded anti-fuse OTP memory Secure OTP is a combined Physical Macro, and Digital RTL providing comprehe…
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
Auxiliary DAC - 12-bit Successive Approximation Register (SAR) DAC
This digital-to-analog converter implements segmented R-2R and thermometer decoder architecture to achieve 12-bit resolution.
The TT-Ascalon™ is an Out-of-Order, superscalar, 8-wide decode processor based on the RISC-V RVA23 profile, co-designed and optim…
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
LPDDR4 multiPHY V2 - UMC 28HPC+18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - TSMC28HPC+18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY - TSMC16FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - TSMC16FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4X multiPHY - TSMC12FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
LPDDR4 multiPHY V2 - TSMC12FFC18
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …
The LPDDR4 multiPHY is the second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) …