ldo IP Listing

RAR-iLR-qLR-ref-1.62-3.63-0.55-2.5.01_TSMC_40_uLPeF is a Retention Alternating Regulator in TSMC 40uLPeF combining two regulation…

• TSMC
• 40nm
• ULP

The IP block provides the physical layer implementation of ISO 14443 interface.

• SMIC
• 180nm
• G

The IP block provides the physical layer implementation of ISO 14443 interface.

• SMIC
• 180nm
• G

The OT1152 is an 80mA CMOS buck regulator designed for use with high input voltages and logic level output voltages..

• GlobalFoundries
• 180nm
• BCD

MIPI ASPMI Slave interface provides full support for the two-wire MIPI ASPMI synchronous serial interface, compatible with SPMI s…

• MIPI

The PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.

• TSMC
• 12nm
• FFC

The PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.

• PCIe Gen5
• TSMC
• 12nm
• FFC

APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50M…

• UMC
• 22nm
• ULP
• Silicon Proven

Over-voltage Protection Module enabling direct connection of voltage regulators to 5.5 V batteries with standard 1.8 V I/O devices

• TSMC
• 22nm
• ULL
• Pre-Silicon

The ODT-AFE-2T2R-GF22FDX is an ultra-highperformance AFE designed in a Global Foundries 22nm process.

• GlobalFoundries
• 22nm
• FDX

The ODT-AFE-1T1R-12 is an ultra-high-performance AFE designed in a 12nm process.

• Analog Front End
• In Development
• Contact Vendor

Over-voltage Protection Module enabling direct connection of voltage regulators to 5.5 V batteries with standard 1.8 V I/O devices

• GlobalFoundries
• 22nm
• FDX
• Pre-Silicon

Combo voltage regulator designed in TSMC 40 ULP, combining a linear regulator for active mode with an ultra-low quiescent regulat…

• TSMC
• 40nm
• ULP
• Pre-Silicon

The ANLBPLL0100 is an integer-N PLL for frequency synthesis that can be used to create a low phase-noise local oscillator (LO) fo…

• GlobalFoundries
• 130nm

Combo voltage regulator designed in TSMC 40 ULP eFlash, combining a linear regulator for active mode with an ultra-low quiescent …

• TSMC
• 40nm
• ULP eFlash
• Pre-Silicon

M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.

• PCIe Gen5

This is the 4th Generation SDR RF IP that would support 2x2 and a frequency ranging from 200MHz to 7.3GHz with a support of up to…

• RF Front End
• In Production
• Immediate

This is the 3rd Generation SDR RF IP that supports 1x1 and a frequency ranging from 100MHz to 2.6 GHz, which is currently in TSMC…

• RF Front End
• In Production
• Immediate

The ShortLink Fractional-N PLL 'SL40LP_2G1PLL_1' is a widely programmable delta sigma frequency synthesizer.

• TSMC
• 40nm
• LP
• Pre-Silicon

Combo voltage regulator designed in TSMC 22ULL, combining a linear regulator for active mode with an ultra-low quiescent regulato…

• TSMC
• 22nm
• ULL
• Pre-Silicon