Vendor: M31 Technology Corp. Category: Single-Protocol PHY

PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation

The PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.

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PCIe Gen5 TSMC 12nm FFC View all specifications

Overview

The PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP supports a complete range of PCIe 5.0 Base applications and is compliant with the PIPE 5.2 specification. The IP integrates high-speed mixed signal circuits to support 32Gbps PCIe 5.0 traffic and is backward compatible with 16 Gbps PCIe 4.0, 8.0Gbps PCIe 3.1, 5.0Gbps PCIe 2.1 and 2.5Gbps PCIe 1.1 data rates. With the support of TX and RX equalization techniques, the PCIe 5.0 IP is designed to meet the requirements of different channel conditions.

Key features

  • Fully compliant with PCI Express Base 5.0 electrical specification
  • Compliant with PIPE5.2 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE5.2 specification
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allow user-specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports robust BIST functions for mass production testing
  • Programmable differential reference clock pad that can receive or transmit 100MHz reference clock
  • Built-in PLL for receiving 25MHz crystal clock and generating 100MHz reference clock for RC applications
  • Built-in LDO for analog core power generation, providing easier IC integration and lower BOM cost for SSD applications
  • Macro-based cells that can be combined into bifurcation applications

Block Diagram

PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC —

Specifications

Identity

Part Number
PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
Vendor
M31 Technology Corp.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen5

Provider

Contact M31 Technology Corp.

Learn more about Single-Protocol PHY IP core

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Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

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Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation?

PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation is a Single-Protocol PHY IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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