The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices.
The PLL resides inside the IO ring that includes two analog power supply pads, occupying no core area.
In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any standard IO pad pitch and can be implemented in staggered and in-line IO configurations.
PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 14 500 MHz Post-Divide Reference frequency FPFD 14 200 MHz VCO Frequency FVCO 3200 MHz Output Frequency FOUT 25 1600 MHz Output Duty Cycle tDO 45 55 % Total area of macro (excluding bond pad area) A 0.02 sq. mm May vary depending on size of IO slots Chip core area requirement CA 0 sq. mm Total Power IDD 3 mA Operational Voltage (Digital) VDIG 0.8 0.9 1.0 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range
