Vendor: Xilinx, Inc. Category: Debug Trace

Virtual Input/Output (VIO)

The LogiCORE™ IP Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in …

Overview

The LogiCORE™ IP Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time. The number and width of the input and output ports are customizable in size to interface with the FPGA design. Because the VIO core is synchronous to the design being monitored and/or driven, all design clock constraints that are applied to your design are also applied to the components inside the VIO core. Run time interaction with this core requires the use of the Vivado® logic analyzer feature.

Key features

  • Provides virtual LEDs and other status indicators through synchronous input ports
  • Includes optional activity detectors on input ports to detect rising and falling transitions between samples
  • Provides virtual buttons and other controls through synchronous output ports
  • Includes custom output initialization that allows you to specify the value of the VIO core outputs immediately following device configuration and start-up.
  • Run time reset of the VIO core to its initial values

Specifications

Identity

Part Number
Virtual Input/Output (VIO)
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about Debug Trace IP

What is Virtual Input/Output (VIO)?

Virtual Input/Output (VIO) is a Debug Trace IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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