VeriSyno Microelectronics Co., Ltd. is a national high-tech enterprise dedicated to the research and development of semiconductor IPs. The company’s main products include mixed-signal high-speed interface IPs such as USB, HDMI, DDR, MIPI, PCIe, SATA, and various analog IPs such as ADC, DAC, PLL, LVDS, as well as independently developed PSRAM interface IO solutions and vMAC series IPs. As one of the important semiconductor IP suppliers in China, in active collaboration with local foundries, VeriSyno has long been committed to the porting of those mature interface IPs to processes such as 22/28/40/55nm, to ensure secure and reliable supply of domestic IPs. The company’s diversified IP products have been widely used in industries such as industrial, medical, AI, and IoT. VeriSyno was established in September 2018 and is headquartered in Hefei, Anhui, with branch offices in Beijing, Shanghai, and Shenzhen.
Our PSRAM solutions cover a range from 400Mbps to 1066Mbps, offering both normal-speed PSRAM digital IP and high-speed PSRAM mixe…
VeriSyno offers a variety of digital IPs tailored to meet the demands of consumer, industrial, and automotive SoCs, enabling effi…
VeriSyno provides a flexible and configurable security IP solution, which includes common symmetric encryption algorithms, random…
Our PSRAM solutions cover a range from 400Mbps to 1066Mbps, offering both normal-speed PSRAM digital IP and high-speed PSRAM mixe…
All self-developed domestic IPs
VeriSyno offers network IP solutions tailored for the high-end server market.
IP
IP
The HDMI Rx PHY is the physical layer of an HDMI receiver.
This IP is composed of a single to sextuple channel 10-bit, 300MHz DAC designed for 40nm CMOS technology supplied at 3.3V.
The HDMI Tx PHY is the physical layer of a single-link HDMI transmitter interface.
The HDMI Rx PHY is the physical layer of an HDMI receiver.
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…
The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …
The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …
The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…
The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two…
The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…