VeriSilicon Microelectronics (Shanghai) Co., Ltd. IP Cores

The present IP devise a Voltage Detector (VDT) circuit.

• Voltage Monitor

The present IP is a Voltage Detector (VDT) circuit.

• Voltage Monitor

The present IP is a VCC Detector (VDT) circuit.

• Voltage Monitor

The USB11PHY is an IP version of USB transceiver.

• UCIe 1.1

The present IP is a Ring Oscillator.

• Oscillator

The present IP is a Ring Oscillator.

• Oscillator

The present IP is a RC oscillator with one external resistor to generate 25~50 MHz clock.

• Oscillator

The present IP is a RC oscillator with one external resistor to generate 25~50 MHz clock.

• Oscillator

Based on GSMC 0.18um 3.3v/1.8v Logic process, current design of the Power Regulator is to provide both 3.3v and 1.8v power suppli…

• LDO Voltage Regulator

Present project is a regulator that generates 1.8v voltage from 3.3v power supply.

• LDO Voltage Regulator

This is a Power-On-Reset circuit that generates a reset pulse when power supply is on.

• Power On Reset (POR)

The present IP is a Power On Reset (POR) circuit without external resistors or capacitors.

• Power On Reset (POR)
• GDS Ready
• Now

This PLL is designed for audio clock generation.

• Clock Generator

This IP is a programmable Analog PLL suitable for high speed clock generation.

• PLL
• GDS Ready
• Now

Present IP is a programmable Analog PLL suitable for high speed clock generation.

• PLL

This IP is a programmable Analog PLL suitable for high speed clock generation.

• Standard Cell Libraries

The GSMC18_PLL_01 is developed as a macro cell for clock generation.

• PLL

To provide a solution to the MMC cards, GSMC18_MMC_03 is consolidated by four independent IPs: GSMC18_PRG_03, GSMC18_ROSC_01, GSM…

• Mixed Signal Subsystem

The USB11PHY is an IP version of USB transceiver.

• UCIe 1.1

This IP is a programmable Analog PLL suitable for high speed clock generation.

• PLL