VeriSilicon Microelectronics (Shanghai) Co., Ltd. (VeriSilicon, 688521.SH) is a leading public company that provides custom silicon solutions, leveraging its comprehensive and proprietary portfolio of semiconductor IPs.
VeriSilicon possesses six categories of in-house processing IPs, namely Graphics Processing Unit (GPU) IP, Neural Network Processing Unit (NPU) IP, Video Processing Unit (VPU) IP, Digital Signal Processing (DSP) IP, Image Signal Processing (ISP) IP, and Display Processing IP, as well as more than 1,700 analog and mixed-signal IPs, RF IPs, and interface IPs.
Leveraging its own IPs, VeriSilicon has developed a wealth of software and hardware custom chip design platforms targeting Artificial Intelligence (AI) applications, covering always-on ultralight spatial computing devices such as smartwatches and AI/AR glasses, high-efficiency edge computing devices such as AI PCs, AI phones, smart cars, and robots, as well as high-performance cloud computing devices like data centers and servers.
In response to the trend of System-on-Chip (SoC) evolving towards System-in-Package (SiP) driven by the demand for large computing power, VeriSilicon put forward the concepts of "IP as a Chiplet”, "Chiplet as a Platform", and "Platform as an Ecosystem”. The company keeps advancing the R&D and industrialization of its Chiplet technologies and projects from the perspective of interface IP, Chiplet architecture, advanced packaging technology, and others for AI-Generated Content (AIGC) and autonomous driving solutions.
Under its unique “Silicon Platform as a Service” (SiPaaS) business model, VeriSilicon serves a broad range of market segments, including consumer electronics, automotive electronics, computer and peripheral, industrial, data processing, Internet of Things (IoT), among others. Its main customers include fabless, IDM, system vendors (OEM/ODM), large internet companies, and cloud service providers.
Founded in 2001 and headquartered in Shanghai, China, VeriSilicon has 9 design and R&D centers, along with 11 sales and customer service offices worldwide. VeriSilicon currently has more than 2,000 employees.
SMIC 0.13um 1.2V Power On Reset
Present Power on Reset generates system reset pulses (POR12) when 1.2V power supplier (VIN12) is turned on.
SMIC 0.13um 3.3V/1.2V Power on Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on.
SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
SMIC 0.13μm 1.62~3.3v->1.2v Power Regulator
Targeted in SMIC 0.13μm 1.2v/3.3v logic process, current design of Power Regulator is to provide 1.2v power supply which is regul…
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for generating system clock.
This PLL is designed for audio clock generation.
SMIC 0.13um 1Channel 10Bit 10MHz DAC
S13V33_R2RDAC_01 is a 10bit@10MHz DAC IP which implements a 7-bit (from D [0] to D [6]) R2R_Ladder and 3-bit thermometer decoder …
IBM 65nm 24-bit Stereo Sigma-Delta ADC
The I65GV25_ADC_01 specifies the design of a high-performance 24-bit stereo Audio ADC for portable digital audio systems.
IBM 65nm 24bit Sigma-Delta DAC
The I65GV25_DAC_01 specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems.
This PLL is designed for audio clock generation.
This analog 2-1 MUX is designed for low speed application.
IBM 65nm 3.3v-1.0v Power Regulator
This IP is a 3.3V to 1.0V power regulator in IBM 65nm 1.0V/2.5V process.
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP is a programmable Analog PLL suitable for high speed clock generation.
IBM10SF 1.0v/2.5v APLL Brief Specification
This IP is a programmable Analog PLL suitable for high speed clock generation.
VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V VPPIO_DUP_01 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing I…
SMIC 0.18um Stereo Speaker Drivers
The SMIC18_SPKDRIVER_01 specifies the design of stereo speaker drivers.
SMIC 0.18¦Ìm 5v-3.3v/1.8v Power Regulator
Based on SMIC 0.18¦Ìm 3.3v/1.8v Logic process, this design of Power Regulator is to provide both 3.3v and 1.8v power supplies whi…