ADC 10-bit pipeline 110Mhz 3.3V
V-Trans Microelectronics
•
HQ:
CHINA
This Analog -to-Digital converter IP has a monolithic differential pipelined architecture with output error correction logic prov…
- 10 Bit
Compare 30 V-Trans Microelectronics IP Cores from 1 vendors
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LVDS Receiver 1250Mb/s, 800Mhz clock
V-Trans Microelectronics• HQ: CHINAV-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high …
- Single-Protocol PHY
- silicon tested by 3rd independent party
- now
- IEEE std 1596.3-1996, ANSI/…
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LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
V-Trans Microelectronics• HQ: CHINAV-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high …
- Single-Protocol PHY
- now
- IEEE std 1596.3-1996 , ANSI…
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Low power 8-bit ADC, 2Mhz , 600uA - 3.3V
V-Trans Microelectronics• HQ: CHINA8-bit ADC in 0.35um HHNEC CZ6H process 600uA @ 2Mhz
- 8 Bit
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Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)
V-Trans Microelectronics• HQ: CHINANow available up to 170 Mhz per channel !
- V-By-One
- pre-silicon
- now
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Audio PLL - Fractional-N ±0.05 ppm accuracy
V-Trans Microelectronics• HQ: CHINAThis PLL can generate all the frequencies used by audio systems from a stable clock of 10 to 40Mhz.
- PLL
- silicon proven
- now
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LVDS serdes 4:28 channel decompression RX 8-150Mhz
V-Trans Microelectronics• HQ: CHINAFPD-LINK 24-bit color, 8-150Mhz Receiver LVDS serdes 4:28 channel decompression RX 56-1050 Mbs x4 V-Trans 's FPD Link Receiver Ma…
- Single-Protocol PHY
- now
- IEEE std 1596.3-1996,ANSI/T…
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LVDS serdes 28:4 channel compression TX 20-170Mhz
V-Trans Microelectronics• HQ: CHINALVDS serdes 28:4 channel compression TX 140-1190 Mbs x4 FPD-LINK Transmitter 24-bit color 20-170Mhz This FPD Link Transmitter Mac…
- Single-Protocol PHY
- now
- IEEE std 1596.3-1996,ANSI/T…
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PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
V-Trans Microelectronics• HQ: CHINAThe VT18PLL500 is a macro cell for clock generation.
- PLL
- silicon proven
- now
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LCD Host LVDS Interface, Dual Pixel 20-112Mhz (SVGA/QXGA)
V-Trans Microelectronics• HQ: CHINAV-Trans 's LVDS Display interface IP is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allo…
- V-By-One
- silicon proven
- now
- openLDI v0.95, LVDS IEEE St…