Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
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With a strong focus on smart energy, industrial IoT, and utility-grade wireless solutions - covering metering, integration of micro generation, field operations, consumer devices, and a cloud-based open-standards for the Internet of Things (IoT) platform, SLS has successfully established as an international technology provider to multiple sectors. SLS has broadened its wings to a global operation across three continents (America, Europe and Asia), which includes more than 250 trained engineering professionals in India and they are responsible for FPGA design, PCB development, prototype development, software development, software applications, and manufacturing. Through long established relationships with organizations such as Altera, Toshiba, Hitachi, Telefonica, Intel, Dell, BHEL and many others, SLS has earned a top-notch reputation as a products and services provider.
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Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite int…
Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI).
The USB 2.0 Host Controller IP Core is a 32-bit Avalon/AXI/AHB interface compliant core and supports ULPI interface.
USB 2.0 Device with FIFO Interface (USB20HF)
USB 2.0 device, FIFO interface (USB20HF) IP Core provides FIFO interface for endpoints and ULPI interface for Host communication.
The SD/eMMC Host Controller IP Core implements the SD Physical Layer v3.0 and eMMC Physical Layer v4.51 compatible Host Controlle…
I²S Controller is designed to transfer audio data to and from Audio codec.
Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface.
USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
The USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon/…
USB 1.1 Device, Software Based Enumeration (USB11SR)
The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface.
The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard.
I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of d…