Logicircuit, Inc. IP Cores

A 32-bit timer module that attaches to the AXI4-Lite interface, can be cascaded to 64-bit.

• Timers & Watchdogs
• March 2014

The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect (to provide a smooth…

• Protocol Bridge
• March 2014

Provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices.

• SPI / QSPI XSPI
• AVAILABLE

Allows the designer to tailor their application by setting certain parameters to enable/disable features.

• Reset Controller
• March 2014

Provides a bidirectional interface between a user IP core and the AXI4 interface standard.

• Protocol Bridge
• March 2014

Concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor.

• Interrupt Controller
• March 2014

Connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices.

• Network-On-Chip
• March 2014

Provides a general purpose input/output interface to the AXI4-Lite interface.

• GPIO
• March 2014

Maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interf…

• Controller

Provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect, optimized for slave operation…

• Protocol Bridge
• AVAILABLE

Implements MIL-STD-1553 serial data bus.

• Mil Std 1553
• 2014

The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification.

• Monitoring
• AVAILABLE