Kintex Ultra Scale Plus NVMe Host IP
Logic Design Solutions
•
HQ:
FRANCE
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
- NVMe Controller
Compare 55 Logic Design Solutions IP Cores from 1 vendors
-
-
AGILEX 7 R-Tile Gen5 NVMe Host IP
Logic Design Solutions• HQ: FRANCEThe LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
- NVMe Controller
-
LDS SATA RECORDER IP ON ARTIX 7
Logic Design Solutions• HQ: FRANCEIP
- SATA Controller
- Good
- Now
-
Dual SATA Host controller on Virtex 5 FXT FPGA
Logic Design Solutions• HQ: FRANCEThe LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
- SATA Controller
- Good
- now
-
Logic Design Solutions• HQ: FRANCE
The LDS SATA RECORDER XV6 IP is a recorder system IP.
- SATA Controller
- Now
-
SATA III HOST Controller on Virtex 6
Logic Design Solutions• HQ: FRANCEThe LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 …
- SATA Controller
- Good
- Now
-
Synchronous Universal Asynchronous Receiver/Transmitter
Logic Design Solutions• HQ: FRANCEThe macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a micr…
- UART
- Now
- DO254
-
SPI Master - EEPROM Controller
Logic Design Solutions• HQ: FRANCEThe MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
- SPI / QSPI XSPI
- Now
-
Logic Design Solutions• HQ: FRANCE
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus.
- I2C / I3C
- Now
-
Logic Design Solutions• HQ: FRANCE
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus.
- I2C / I3C
- Now
-
Logic Design Solutions• HQ: FRANCE
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus.
- I2C / I3C
- Now
-
ARINC 429 Synchronous Transmitter Receiver
Logic Design Solutions• HQ: FRANCEThe M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CP…
- ARINC 429
- Now
-
Serial protocol Interface Slave
Logic Design Solutions• HQ: FRANCEThe MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.
- SPI / QSPI XSPI
- Now
-
Universal Asynchronous Receiver Transmitter
Logic Design Solutions• HQ: FRANCEThe macro M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
- UART
- Now
-
Universal Asynchronous Receiver / Transmitter
Logic Design Solutions• HQ: FRANCEThe macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
- UART
- Now
-
SATA Device Controller on Kintex 7
Logic Design Solutions• HQ: FRANCEThe LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex…
- SATA Controller
-
SATA Host Controller on Spartan 6 LXT FPGA
Logic Design Solutions• HQ: FRANCEThe LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA.
- SATA Controller
- Good
- Now
-
Logic Design Solutions• HQ: FRANCE
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA S…
- SATA Controller
- Good
- Now
-
SATA Host controller on Virtex 5 FXT
Logic Design Solutions• HQ: FRANCEThe LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
- SATA Controller
- Good
- Now
-
Serial ATA Dual Host Controller
Logic Design Solutions• HQ: FRANCEThe LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
- SATA Controller
- Good
- Now
- SATA II