Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process mask programmable cell array with body E Core Cell Library.
- UMC
- 180nm
- G
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.15um SP process
UMC 0.15um SP Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um Logic high speed(FSG) process, Metal programmable(M3/M4/M5) cell array Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um SP process
UMC 0.13um SP/FSG Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL/FSG process
UMC 0.13um LL Logic(FSG) process metal programmable (M3/M4/M5) cell array standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL process, standard Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL FSG process high density Generic Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process metal programmable (M3/M4/M5) cell array standard Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process mask programmable cell array with body E Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high density Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process high performance Core Cell Library.
Standard Cell (Generic) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL Logic Low-K RVT process standard Core Cell Library.
Standard Cell (Generic) Library IP, RVT, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process Standard Cell Library.
Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 9-Track Standard Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C35).
Standard Cell (Generic) Library IP, RVT, 7 tracks, UMC 28nm HPC process
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library (C30).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 12-Track Standard Generic Core Cell Library (C30).