Two Port Register File Compiler IP, UMC 40nm LP process
Faraday Technology
•
HQ:
Taiwan
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature.
- UMC
- 40nm
- LP
Compare 2,534 Faraday Technology IP Cores from 1 vendors
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Two Port Register File Compiler IP, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/LVT process, Two Port Register File with LVT.
- UMC
- 40nm
- LP
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Two Port Register File Compiler IP, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/ Low-K process, Two Port Register File memory compiler.
- UMC
- 40nm
- LP
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Two Port Register File Compiler IP, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP peripheral LVT Two Port Register File memory compiler.
- UMC
- 28nm
- HLP
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Two Port Register File Compiler IP, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/ Low-K Two Port Register File compiler.
- UMC
- 28nm
- HLP
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Two Port Register File Compiler IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
- UMC
- 250nm
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Two Port Register File Compiler IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process synchronous Two Port Register File compiler.
- UMC
- 250nm
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Two Port Register File Compiler IP, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanUMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
- UMC
- 180nm
- G
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Two Port Register File Compiler IP, UMC 0.13um LL process
Faraday Technology• HQ: TaiwanUMC 0.13um LL Logic/FSG process high density synchronous Two Port Register File SRAM memory compiler.
- UMC
- 130nm
- LL
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Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um Logic HS FSG Synchronous high density Low Power Two Port Register File SRAM memory compiler.
- UMC
- 130nm
- HS
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Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um HS/FSG Logic process Synchronous Two Port Register File SRAM memory compiler.
- UMC
- 130nm
- HS
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Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um HS/LL fusion (FSG) process high density synchronous Two Port Register File SRAM memory compiler.
- UMC
- 130nm
- HS
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Two Port Register File Compiler IP, UMC 0.11um LL/FSG process
Faraday Technology• HQ: TaiwanUMC 0.11um Logic(LL) FSG process synchronous Two Port Register File memory compiler.
- UMC
- 110nm
- LL
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Two Port Register File Compiler IP, UMC 0.11um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.11um HS Logic process synchronous Two Port Register File SRAM memory compiler.
- UMC
- 110nm
- HS
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Two Port Register File Compiler IP, UMC 0.11um HS/AE process
Faraday Technology• HQ: TaiwanUMC 0.11um HS/AE (AL Enhancement) Logic process synchronous Two Port Register File memory compiler.
- UMC
- 110nm
- HS
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Two Port Register File Compiler IP, UMC 0.11um eFlash/HS process
Faraday Technology• HQ: TaiwanUMC 0.11um eFlash HS process, Two Port Register File.
- UMC
- 110nm
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Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process
Faraday Technology• HQ: TaiwanUMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library.
- UMC
- 55nm
- SP
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Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process
Faraday Technology• HQ: TaiwanUMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
- UMC
- 28nm
- HPC
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Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38).
- UMC
- 28nm
- HLP
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Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT).
- UMC
- 28nm
- HLP