Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process
Faraday Technology
•
HQ:
Taiwan
UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35).
- UMC
- 28nm
- HLP
Compare 2,534 Faraday Technology IP Cores from 1 vendors
-
-
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process
Faraday Technology• HQ: TaiwanUMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35).
- UMC
- 28nm
- HPC
-
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38).
- UMC
- 28nm
- HLP
-
Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30).
- UMC
- 28nm
- HLP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library.
- UMC
- 28nm
- HLP
-
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HPC process
Faraday Technology• HQ: TaiwanUMC 28nm HPC/HVT Logic and Mixed-Mode process 7-Track POWERSLASH Kit Cell Library C35.
- UMC
- 28nm
- HPC
-
Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process
Faraday Technology• HQ: TaiwanUMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
- UMC
- 28nm
- HLP
-
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/RVT Low-K Logic process 12-Track high performance Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell (Ultra High Speed) Library IP, LVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/LVT Low-K Logic process 12-Track high performance Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 40nm LP process
Faraday Technology• HQ: TaiwanUMC 40nm LP/HVT Low-K Logic process 12-Track Standard Cell Library.
- UMC
- 40nm
- LP
-
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um HS/FSG process
Faraday Technology• HQ: TaiwanUMC 0.13um HS/FSG Logic process high density Core Cell Library.
- UMC
- 130nm
- HS
-
Standard Cell (Generic) Library IP, 10-track, RVT, UMC 90nm SP process
Faraday Technology• HQ: TaiwanUMC 90nm SP Logic Low-K process standard Core Cell Library.
- UMC
- 90nm
- SP
-
Standard Cell (Generic) Library IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process standard Cell Library.
- UMC
- 250nm
-
Standard Cell (Generic) Library IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process standard Cell Library.
- UMC
- 250nm
-
Standard Cell (Generic) Library IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process mask programmable cell array with body E Core Cell Library.
- UMC
- 250nm
-
Standard Cell (Generic) Library IP, UMC 0.25um process
Faraday Technology• HQ: TaiwanUMC 0.25um Logic process shrink (0.22um) mask programmable cell array with body A Core Cell Library.
- UMC
- 250nm
-
Standard Cell (Generic) Library IP, UMC 0.18um MS process
Faraday Technology• HQ: TaiwanUMC 0.18um Mixed-Mode / RFCMOS process standard Core Cell Library.
- UMC
- 180nm
- MS
-
Standard Cell (Generic) Library IP, UMC 0.18um LL process
Faraday Technology• HQ: TaiwanUMC 0.18um LL Logic process mask programmable cell array with body E Core Cell Library.
- UMC
- 180nm
- LL
-
Standard Cell (Generic) Library IP, UMC 0.18um LL process
Faraday Technology• HQ: TaiwanUMC 0.18um LL Logic process standard Core Cell Library.
- UMC
- 180nm
- LL
-
Standard Cell (Generic) Library IP, UMC 0.18um G2 process
Faraday Technology• HQ: TaiwanUMC 0.18um GII Logic process standard Core Cell Library.
- UMC
- 180nm
- G