Overview
The USB4 PHY IP provides designers with the industry's best combination of small area and low power with support for the leading process technologies such as 5nm FinFET. The USB4 PHYs use a single efficient GDSII design that supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates.
The USB4 IP is designed to meet the functionality, power, performance, and area requirements of a broad range of storage, PC, and tablet SoC designs as well as software development debug and easy deployment of artificial intelligence (AI) applications at the edge.
The USB IP has shipped in billions of units for leading electronics companies worldwide. Using the USB IP significantly reduces development time and engineering risk, helping designers to bring USB-based SoCs to market faster.
The USB IP is the most certified IP solution in the industry. As the leading provider of USB IP for nearly two decades, the vendor is enabling designers to lower the risk and adoption barrier of integrating USB4 functionality into their SoCs.
Learn more about Single-Protocol PHY IP core
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
