Vendor: T2M GmbH Category: Multi-Protocol PHY

USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC

The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support…

UMC 28nm HPC In Production View all specifications

Overview

The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support of PIPE v4.4 interface spec, Universal Serial Bus (USB) compliant with the USB 3.2, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.2 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios.

Key features

  • Compliant with PCIe 3.1 Base Specification
  • Compliant with Universal Serial Bus 3.2 Specification
  • Compliant with Universal Serial Bus 2.0 Specification
  • Compliant with UTMI 1.05 Specification
  • Compliant with SATA 3.2 Specification
  • Compliant with PIPE 4.4
  • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s (PCIe)
  • Supported data transfer rate: 5.0 GT/s and 10.0 GT/s (USB)
  • Supported data transfer rate: 1.5 GT/s, 3.0 GT/s and 6.0 GT/s (SATA)
  • High-speed data transfer rate: 480 Mbps (USB)
  • Full-speed data transfer rate: 12 Mbps (USB)
  • Supported physical lane width: x2
  • Supported parallel interface: 32-bit
  • Supported input reference clock: 100 MHz (PCIe)
  • Supported input crystal clock for SRIS: 25 MHz
  • Support crystal-less in SATA mode
  • Support low power operation with configurable setting in power state:
  • PLL control, reference clock control, and embedded power gating control
  • UMC 28nm HPCP 1P9M4X2Y2R_AL=28kA (uHVT/HVT/RVT/LVT) process
  • Operating Voltage: 0.9V, 0.95V, 1.8V and 3.3V
  • Providing robust testability by low cost Build-In-
  • Self-Test (BIST) and near/far end loopback at analog/digital interface
  • Silicon Proven in UMC 28HPC

Block Diagram

USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP in 28HPC block diagram

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Synopsys library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Multi-Protocol PHY IP core

Frequently asked questions about Multi-Protocol PHY IP cores

What is USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC?

USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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