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Vendor:
Synopsys, Inc.
Category:
Single-Protocol PHY
USB 3.1 PHY (10G/5G) - SS 10LPP x1 OTG, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
Overview
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the leading process technologies to 5nm. Both the USB-C 3.1 and USB 3.1 PHYs use a single efficient GDSII design that supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes. To maximize battery life in mobile applications, the DesignWare USB-C/USB 3.1 PHYs are designed to minimize power consumption and standby current. In addition, the DesignWare USB-C 3.1 femtoPHY is optimized to support the USB Type-C connectivity specification.
The USB IP is the most certified USB IP solution in the industry. With over 3,000 design wins and approximately three billion silicon-proven units shipped, the vendor's complete USB IP solution, consisting of digital controllers, PHYs, verification IP, IP Prototyping Kits and IP software development kits, enables designers to lower integration risk and speed time-to-market.
Key features
- Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
- USB-C 3.1 PHY IP supports USB Type-C specification
- Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
- Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
- Design minimizes area and power
Block Diagram
dwc_usb31sspphy_ss10lppx1ns block diagram
Specifications
Identity
Part Number
dwc_usb31sspphy_ss10lppx1ns
Vendor
Synopsys, Inc.
Type
Silicon IP
Standards & Interfaces
Supported Standards
USB 3.1
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is USB 3.1 PHY (10G/5G) - SS 10LPP x1 OTG, North/South Poly Orientation?
USB 3.1 PHY (10G/5G) - SS 10LPP x1 OTG, North/South Poly Orientation is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.