Overview
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering consists of Host, Device, and Dual-Role Device controllers, PHYs with and without support for the USB Type-C™ connectivity specification and DisplayPort 1.3 support, verification IP, IP Prototyping Kits, and IP software development kits. These elements enable quick development of advanced chip designs incorporating the 10 Gbps SuperSpeed USB standard. The Synopsys USB 3.1 IP is targeted for integration into SoCs for media storage, creation, and playback devices, requiring faster bandwidth between PCs and portable electronic devices. Optimized for low power, the Synopsys USB 3.1 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The Synopsys USB 3.1 IP enables the fastest SuperSpeed USB data transfer speeds while lowering overall power consumption. As the leading supplier of USB IP, Synopsys provides designers with a high-performance, low-power, and area-efficient IP solution, for cost-effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB enables us to build a low risk, high quality SuperSpeed USB IP solution.
Learn more about Single-Protocol PHY IP core
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
