Overview
The USB 2.0 Type-C IP solution for IoT applications includes controllers and PHYs optimized for cost-sensitive and energy-efficient IoT edge applications.
Based on the USB 2.0 IP that has been certified more than 90 times and integrated in thousands of SoCs, the DesignWare USB 2.0 Type-C IP cuts silicon area by up to 50% compared to competitive offerings, saving on average $0.03 per die.
To extend battery life, the USB IP uses 30% lower active power compared to competing solutions and near 0W of standby power. The DesignWare USB 2.0 Type-C IP supports the Unified Power Format (UPF) standard, which speeds implementation and testing of power domains. For the fastest, most efficient development, the IP eliminates the 80% of standard USB 2.0 configuration options that are not essential to IoT systems.
In addition to the DesignWare USB 2.0 Type-C Controllers and PHYs, the vendor offers USB IP prototyping kits, IP software development kits and verification IP to enable early software development, reduce IP integration risk and speed time-to-market.
Learn more about Single-Protocol PHY IP core
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
