Vendor: T-Head Category: CPU

Ultra-low power processor with RISC-V architecture possessing secure execution capability

E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency.

RISC-V View all specifications

Overview

E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency. It can be further equipped with secure execution technology to enhance system security. It is suitable for application fields that are extremely sensitive to power consumption and cost, such as IoT and MCU.

Key features

  • Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC);
  • Pipeline: 2-stage;
  • Permission mode: Optional M state or M+U state;
  • General register: 16 32-bit GPRs;
  • Bus interface: Dual bus (instruction bus + data bus);
  • Memory protection: 0 to 16 optional protection zones;
  • Tight coupling IP: Interrupt controller and timer;
  • Multiplier: Optional slow multiplier and fast multipliers.
  • Secure execution technology: Resists any hardware and software attack, and increases system security;
  • Low-power cache: Reduces system memory access latency, and improves memory efficiency;
  • Dynamic adjustment of interrupt priority: Enhancing real-time system performance, and implementing interrupt priority inversion in specific scenarios;
  • Single-cycle memory speculation execution: Makes full use of memory bandwidth, so that the processor is completely streamlined.

Block Diagram

E902 block diagram

Applications

  • Wireless Connectivity;
  • Industrial Control

Specifications

Identity

Part Number
E902
Vendor
T-Head
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T-Head
HQ: China

Frequently asked questions about CPU IP cores

What is Ultra-low power processor with RISC-V architecture possessing secure execution capability?

Ultra-low power processor with RISC-V architecture possessing secure execution capability is a CPU IP core from T-Head listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

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