Vendor: T-Head Category: CPU

Ultra-low power processor with RISC-V architecture possessing secure execution capability

E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency.

Overview

E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency. It can be further equipped with secure execution technology to enhance system security. It is suitable for application fields that are extremely sensitive to power consumption and cost, such as IoT and MCU.

Key features

  • Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC);
  • Pipeline: 2-stage;
  • Permission mode: Optional M state or M+U state;
  • General register: 16 32-bit GPRs;
  • Bus interface: Dual bus (instruction bus + data bus);
  • Memory protection: 0 to 16 optional protection zones;
  • Tight coupling IP: Interrupt controller and timer;
  • Multiplier: Optional slow multiplier and fast multipliers.
  • Secure execution technology: Resists any hardware and software attack, and increases system security;
  • Low-power cache: Reduces system memory access latency, and improves memory efficiency;
  • Dynamic adjustment of interrupt priority: Enhancing real-time system performance, and implementing interrupt priority inversion in specific scenarios;
  • Single-cycle memory speculation execution: Makes full use of memory bandwidth, so that the processor is completely streamlined.

Block Diagram

Applications

  • Wireless Connectivity;
  • Industrial Control

Specifications

Identity

Part Number
E902
Vendor
T-Head
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: China

Learn more about CPU IP core

Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era

For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.

Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection

Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.

Frequently asked questions about CPU IP cores

What is Ultra-low power processor with RISC-V architecture possessing secure execution capability?

Ultra-low power processor with RISC-V architecture possessing secure execution capability is a CPU IP core from T-Head listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP