Vendor: Arasan Chip Systems Inc. Category: UFS Controller

UFS 2.1 Host Controller IP

The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems.

Overview

The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.

UFS 2.1 introduces new extensions to UFS 2.0

  • Support for multiple initiators for a UFS target device
  • Support for CMD priority for UPIUs
  • Support for FFU (Field Firmware Update) using Write buffer SCSI CMD
  • Support for data count (update in UPIU field) in terms of block size

The UFS 2.1 Host controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. There is a Host controller state machine and a FIFO to buffer data in each direction. The processor accesses the Host registers and DMA engine over the AXI or other interface. Transfers are initiated by the UFS driver which also writes the UFS 2.1 Host Controller Interface (UFSHCI) registers to manage Host operation.

Key features

  • JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
  • Supports high performance M-PHY v3.0 type-1
  • 2 lanes @ 5.9 Gbps per lane
  • UniPro v1.6 link layer
  • Definable write-protect group size
  • Boot mode operation
  • Device enumeration and discovery
  • Background operation
  • Secure Erase and Trim operations enhance security
  • Write-protect options include permanent and power-on protection

Block Diagram

Benefits

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

What’s Included?

  • Synthesizable Verilog RTL of the IP Core
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents
  • Gate count estimates available upon request

Specifications

Identity

Part Number
UFS 2.1 Host Controller IP
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about UFS Controller IP core

The Future of Storage: From eMMC to the Blazing Speeds of UFS 5.0

In the world of mobile and embedded electronics, storage is no longer just about capacity; it’s about how fast that data can move. As we transition into an era of on-device AI and 8K video, the standards we rely on—UFS, eMMC, and NAND—are evolving rapidly.

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Vertically Integrated MIPI Solutions

The emerging MIPI standards are designed to ensure interoperability among devices and software that are used in products for the exploding hand-held market. The standards facilitate the interconnection of multiple, mixed-signal integrated circuit devices on a single hand-held product. Use of the standards ensures low power, low pin count and interoperability of all the devices in the system and easy integration.

Design & Verify Virtual Platform with reusable TLM 2.0

As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors Ltd. for the development of a generic Virtual Platform using TLM 2.0; reusable for any system model.

Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP

With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.

Frequently asked questions about UFS Controller IP

What is UFS 2.1 Host Controller IP?

UFS 2.1 Host Controller IP is a UFS Controller IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this UFS Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UFS Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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