UFS 2.1 Host Controller IP

The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.

UFS 2.1 introduces new extensions to UFS 2.0

• Support for multiple initiators for a UFS target device
• Support for CMD priority for UPIUs
• Support for FFU (Field Firmware Update) using Write buffer SCSI CMD
• Support for data count (update in UPIU field) in terms of block size

The UFS 2.1 Host controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. There is a Host controller state machine and a FIFO to buffer data in each direction. The processor accesses the Host registers and DMA engine over the AXI or other interface. Transfers are initiated by the UFS driver which also writes the UFS 2.1 Host Controller Interface (UFSHCI) registers to manage Host operation.

• JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
• Supports high performance M-PHY v3.0 type-1
• 2 lanes @ 5.9 Gbps per lane
• UniPro v1.6 link layer
• Definable write-protect group size
• Boot mode operation
• Device enumeration and discovery
• Background operation
• Secure Erase and Trim operations enhance security
• Write-protect options include permanent and power-on protection

• RMM-compliant synthesizable RTL design in Verilog
• Easy-to-use test environment
• Synthesis scripts
• Technical documents

• Synthesizable Verilog RTL of the IP Core
• Easy-to-use test environment
• Synthesis scripts
• Technical documents
• Gate count estimates available upon request