UFS 2.1 Device Controller IP
The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems.
Overview
The Universal Flash Storage (UFS) is a JEDEC data transfer standard is designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, laptop PCs, DSC, PMP, MP3 and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. UFS transfers follow the SCSI model, but with a subset of SCSI commands.
UFS 2.1 introduces new extensions to UFS 2.0
- Support for multiple initiators for a UFS target device
- Support for CMD priority for UPIUs
- Support for FFU (Field Firmware Update) using Write buffer SCSI CMD
- Support for data count (update in UPIU field) in terms of block size
The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification. The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.
Key features
- Compliant with the following specifications
- ESD220B UFS 2.0 compliant
- MIPI UniPro version 1.6
- Interface supported
- AXI
- Optional AHB, OCP
- High-performance M-PHY v3.0 type 1
- Core features
- 2 lanes @ 5.9 Gbps per lane
- Low power with multiple power operating modes
- Configurable Transmit and Receive FIFOs
- Error detection and reporting. Support Data and Task management
- Support for multiple commands and tasks
Block Diagram
Benefits
- RMM-compliant synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
What’s Included?
- Verilog HDL of the IP Core
- Technical documents
- Gate count estimates available upon request
- Easy to use test environment
- Synthesis scripts
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about UFS Controller IP core
UFS Goes Mainstream
Universal Flash Storage: Mobilize Your Data
Vertically Integrated MIPI Solutions
Design & Verify Virtual Platform with reusable TLM 2.0
Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
Frequently asked questions about UFS Controller IP
What is UFS 2.1 Device Controller IP?
UFS 2.1 Device Controller IP is a UFS Controller IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this UFS Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UFS Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.