Overview
Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using the UDP protocol. The IP core is highly configurable and optimally implemented for the use in current Altera® and Xilinx® FPGA architectures. It provides a simple to use interface to the user logic, and supports the common media independent interfaces MII, RMII, GMII and RGMII. With its 8-bit wide transmit and receive interfaces running at 125 MHz, the IP core is able to operate at full 1 Gbit/sec wire speed. 100 Mbit/sec and 10 Mbit/sec operation is also supported.
Learn more about Ethernet IP core
Humanoid robots are moving from research demos toward real products, and the network inside them is becoming the hard problem. Single Pair Ethernet and Time-Sensitive Networking are emerging as the answer, and CAST already builds the IP cores that make it deterministic.
The evolution to centralized vehicle computing is driving new connectivity requirements. Discover how SerDes supports high-speed sensor data streaming while reducing system complexity.
Building on its High-Speed Ethernet controller IP family, Cadence provides ESUN-ready controller IP for next-generation AI scale-up networking.
This blog post explores how the team verified a 10BASE-T1S automotive ethernet subsystem using a Cadence tools-based multi-platform verification, which unifies simulation, emulation, and formal verification techniques.
Learn how ESUN enhances Ethernet for lossless, predictable AI scale-up networking—cutting overhead, reducing tail latency, and improving efficiency.
Ethernet has evolved significantly from 10 Mbps shared media to today’s multi-hundred gigabit high-speed links. One foundational feature that has enabled this scalability and ease of deployment is Auto-Negotiation (AN).
