Vendor: Enclustra GmbH Category: Ethernet

UDP/IP Ethernet IP Core

Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using…

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Overview

Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using the UDP protocol. The IP core is highly configurable and optimally implemented for the use in current Altera® and Xilinx® FPGA architectures. It provides a simple to use interface to the user logic, and supports the common media independent interfaces MII, RMII, GMII and RGMII. With its 8-bit wide transmit and receive interfaces running at 125 MHz, the IP core is able to operate at full 1 Gbit/sec wire speed. 100 Mbit/sec and 10 Mbit/sec operation is also supported.

Key features

  • Operates at full 1Gbit/sec wire speed
  • Complete UDP, IPv4 and Ethernet layer processing
  • Automatic ARP reply generation
  • Header pass-through mode:
    • Selectively override default UDP/IP/ETH header field values with values embedded in the transmit data stream
    • Selectively embed UDP/IP/ETH header field values in the receive data stream for easy delivery to the user application
  • 1 Gbit/sec, 100 Mbit/sec and 10 Mbit/sec operation
  • MII, RMII, GMII and RGMII media independent interfaces (full-duplex only)
  • Destination UDP port, destination IP address and destination MAC address filtering
  • UDP checksum calculation and check
  • Ethernet frame check
  • Multiple UDP ports with dedicated receive and transmit interfaces for each port
  • Optional receive data buffers
  • Raw Ethernet port for non-UDP communication

Block Diagram

UDP/IP Ethernet block diagram

Benefits

  • Standard UDP communication with FPGA-based systems
  • Full 1 Gbit/sec wire speed can be achieved
  • Low FPGA resource usage

Applications

  • Test and measurement
  • Communication
  • Automation
  • Embedded processing
  • Medical diagnostics

What’s Included?

  • UDP/IP Ethernet IP Core
    • VHDL source files (plain or encrypted, depending on product options)
    • Precompiled ModelSim® simulation libraries
    • User manual (PDF download)
  • UDP/IP Ethernet IP core reference design
    • Reference design top-level VHDL file (plain VHDL)
    • UCF / XDC / SDC constraint files (depending on product options)
    • Xilinx Vivado™ / Altera® Quartus® II project files (depending on product options)
    • Top-level simulation test bench file (plain VHDL)
    • Top-level simulation ModelSim project file
    • Documentation (integrated in UDP/IP/ETH IP core user manual)

Specifications

Identity

Part Number
UDP/IP Ethernet
Vendor
Enclustra GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Enclustra GmbH
HQ: Switzerland
Enclustra is a dynamic, innovative and successful FPGA design service company located in Technopark Zurich, Switzerland. With the FPGA Design Center, Enclustra provides services covering the whole range of FPGA-based system development: From high-speed hardware or HDL firmware through to embedded software, from specification and implementation through to prototype production. In the FPGA Solution Center, Enclustra develops and markets highly-integrated FPGA modules and FPGA-optimized IP cores. By specializing in forward-looking FPGA technology, and with a broad application knowledge, Enclustra can offer ideal solutions at minimal expense in many areas.
Contact Enclustra GmbH

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Frequently asked questions about Ethernet IP cores

What is UDP/IP Ethernet IP Core?

UDP/IP Ethernet IP Core is a Ethernet IP core from Enclustra GmbH listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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