Overview
IGMSLRV01A is a synchronous SVT / LVT periphery ultra high density one port register file compiler. It is developed with TSMC 16 nm 0.8 V/1.8 V CMOS LOGIC FinFET Compact Process. Different combinations of words, bits, and column-selected number (MUX) could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMSLRV01A compiler is capable of providing suitable synchronous SRAM instances models within minutes. It is capable of automatically generating the datasheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold time and minimum high/low pulse width requirements are satisfied. This allows a more flexible clock falling edge during each operation.
Learn more about Register File IP core
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