Muse Semiconductor and True Circuits Announce New IP Access Program Offering High-quality PLLs to Universities at Low Cost
Students and researchers now have easy access to quality IP and MPW services through Muse
Vendor:
True Circuits, Inc.
Category:
PLL
TSMC CL018LP 180nm Deskew PLL - 90MHz-450MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
Overview
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.
Key features
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
What’s Included?
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | 0_18um 1800 nm | — |
Specifications
Identity
Part Number
TCI-T18LP-DSMPLL
Vendor
True Circuits, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about PLL IP core
True Circuits Announces the JSPICE™ Design Environment (JDE™) will be Offered to the JDE Ecosystem Open Source
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) and developer of computer aided design (CAD) software announced today its intention to donate the JSPICE Design Environment (JDE) to form the foundation of a modern AMS development environment that unifies design generation, simulation, measurement, characterization, data analysis, and AI-assisted engineering into a single extensible environment.
True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL
The Ultra+ PLL is designed as an ultra-low jitter, extremely wide range clock multiplier with precise fractional frequency control and optional spread spectrum capability, giving chip designers the ultimate in performance, features and ease of use.
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
At the 62nd Design Automation Conference (DAC), True Circuits will introduce an improved, state-of-the-art digital LC PLL that includes an innovative digital control algorithm that cuts the lock time by as much as 70% over previous versions, while directly controlling the loop bandwidth accurately (by 0.1% of Fref or better) and consistently across PVT variations through continuous background loop-gain calibration.
True Circuits Introduces the JSPICE™ Design Environment (JDE™) at the Design Automation Conference
TCI will introduce its powerful JSPICE™ Design Environment (JDE™) which has been used by True Circuits over the last 26 years to create complex analog and digital IP and will now be available to the public through a membership program.
True Circuits Attends 60th Design Automation Conference, Celebrates 25 Years of Timing Excellence
At the 60th Design Automation Conference (DAC), TCI will introduce its powerful JSPICE™ simulation and design environment which has been used by True Circuits over the last 25 years to create complex analog and digital IP and will now be available to the public initially through a beta test.
Frequently asked questions about PLL IP cores
What is TSMC CL018LP 180nm Deskew PLL - 90MHz-450MHz?
TSMC CL018LP 180nm Deskew PLL - 90MHz-450MHz is a PLL IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.