Vendor: Siemens Tessent Embedded Analytics Category: Debug Trace

Tessent Automotive IC debug and optimization

Vehicles are becoming complex systems approaching billions of lines of code.

Overview

Vehicles are becoming highly complex systems approaching billions of lines of code.

Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, debug and software engineers can observe what’s happening in the design when operational software is running on the system. The instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

Key features

  • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
  • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
  • Status Monitors provides embedded logic analyzer capability
  • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
  • Static instrumentation provides a nonintrusive mechanism for conde instrumentation.
  • Direct Memory Access (DMA) analytic module provide direct memory access to system memory from debug host.

Benefits

  • Observe if your Automotive SoC with massive parallelism behaves as it was meant to
  • Slash your escalating SoC validation costs
  • Identify and resolve errors and bugs significantly faster compared to traditional software-only solutions
  • Root-cause performance degradations and memory corruption

What’s Included?

  • Parameterized soft core (Verilog RTL)
  • Available UVM verification IP
  • Optional Tessent SystemInsight IDE software
  • Optional Tessent Embedded SDK software development kit

Specifications

Identity

Part Number
Tessent Automotive IC debug and optimization
Vendor
Siemens Tessent Embedded Analytics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Debug Trace IP core

Debugging complex RISC-V processors

To debug and profile a RISC-V processor that comprises tens or hundreds of cores and processes billions of instructions each second can be challenging. Is the software running as expected? Does the verification team see the same behavior as the firmware engineers or application developers?

Frequently asked questions about Debug Trace IP

What is Tessent Automotive IC debug and optimization?

Tessent Automotive IC debug and optimization is a Debug Trace IP core from Siemens Tessent Embedded Analytics listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP