Vendor: Exostiv Labs Category: Debug Trace

Deep capture / high visibility Debug IP for Xilinx FPGA

The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…

Overview

The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA. The EXOSTIV IP core uses the FPGA transeivers as a high bandwidth channel to an external memory (in EXOSTIV Probe). The IP includes many advanced features for extending visibility on FPGA running at speed of operation- including data group definition and multiplexing, boolean trigger equations, data qualification (data filtering) and edge transition triggers. Because EXOSTIV IP core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components inside IP Core. EXOSTIV IP can be inserted at RTL level or automatically in the design netlist, thanks to the accompanying EXOSTIV Dashboard software integration with the FPGA vendor tool.

Key features

  • Configurable upstream link, up to 4 transceivers at 12.5 Gbps each.
  • Downstream link to configure IP triggers and data group selection without the need to re-implement the instrumented design.
  • Up to 16 configurable 'Capture Units'
  • Up to 16 multiplexed Data Groups per Capture Unit
  • Up to 2,048 nodes per Data Group
  • Up to 32k simultaneously observable nodes
  • Multi-clock domain support
  • Cross-capture unit trigger lines

Block Diagram

EXOSTIV IP for Xilinx FPGA block diagram

Benefits

  • Extreme visbility on FPGA running at speed of operation
  • Flexible IP insertion options: in RTL or automatically in target design netlist (after synthesis)
  • Efficient use of FPGA resources: the impact on the FPGA memory does not grow with the size of the capture.
  • Extended visibility over time - with the proper settings, the capture can span to hours of real FPGA operating times, from start to end (interrupted capture mode)
  • Real-world visibility level with a total of 8 GB of trace for a single capture.

Applications

  • FPGA debug and verification

What’s Included?

  • Complete FPGA debugging solution, including EXOSTIV Dashboard software (Linux, Windows, Mac) for EXOSTIV IP setup and insertion - and for EXOSTIV IP control for trace data extraction at run-time.
  • Includes EXOSTIV Probe for data extraction from target FPGA at run-time.
  • Includes terabyte-capable Myriad waveform viewer.

Specifications

Identity

Part Number
EXOSTIV IP for Xilinx FPGA
Vendor
Exostiv Labs
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Exostiv Labs
HQ: Belgium

Learn more about Debug Trace IP core

Frequently asked questions about Debug Trace IP

What is Deep capture / high visibility Debug IP for Xilinx FPGA?

Deep capture / high visibility Debug IP for Xilinx FPGA is a Debug Trace IP core from Exostiv Labs listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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