Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: ROM

VeriSilicon SMIC 0.18um LL Pro Syn. LP VROM Compiler, Memory Array Range:128 to 2Mega Bits

VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Programmable Low Power Via1 ROM compiler optimized for Semiconductor Manu…

SMIC 180nm G Pre-Silicon View all specifications

Overview

VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Programmable Low Power Via1 ROM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying Low Power, Low Leakage and speed requirements, it has been optimized for area efficiency. VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Low Power Via1 ROM compiler uses three metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.

Key features

  • Low Power
  • Low Leakage
  • High Density
  • Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
  • Automatic Power Down

Silicon Options

Foundry Node Process Maturity
SMIC 180nm G Pre-Silicon

Specifications

Identity

Part Number
SMIC18LL_LPVROM_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about ROM IP core

VeriSilicon and Google Jointly Launch Open-Source Coral NPU IP

The Coral NPU is built on the open RISC-V instruction set architecture, featuring native tensor processing capabilities, supporting mainstream machine learning frameworks such as JAX, PyTorch, and TensorFlow Lite (TFLite), and utilizing open-standard tools like Multi-Level Intermediate Representation (MLIR) from the Low Level Virtual Machine (LLVM) project for compiler infrastructure.

Frequently asked questions about ROM IP cores

What is VeriSilicon SMIC 0.18um LL Pro Syn. LP VROM Compiler, Memory Array Range:128 to 2Mega Bits?

VeriSilicon SMIC 0.18um LL Pro Syn. LP VROM Compiler, Memory Array Range:128 to 2Mega Bits is a ROM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.

How should engineers evaluate this ROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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