Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: ROM

VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits

VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corp…

Overview

VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/Analog 1P6M Industry Baseline Generic (IBG) 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying Low Power and speed requirements, it has been optimized for area efficiency. VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM compiler uses three metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.

Key features

  • Low Power
  • High Density
  • Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
  • Automatic Power Down

Specifications

Identity

Part Number
GSMC18_LPVROM_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about ROM IP core

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Frequently asked questions about ROM IP cores

What is VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits?

VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits is a ROM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this ROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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