Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: ROM

VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits

VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corp…

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Overview

VeriSilicon GSMC 0.18um Synchronous Programmable Low Power Via1 ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/Analog 1P6M Industry Baseline Generic (IBG) 1.8/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying Low Power and speed requirements, it has been optimized for area efficiency. VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM compiler uses three metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.

Key features

  • Low Power
  • High Density
  • Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
  • Automatic Power Down

Specifications

Identity

Part Number
GSMC18_LPVROM_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Contact VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Learn more about ROM IP core

An MLC ROM With Inserted Redundancy and Novel Sensing Scheme

An Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 16M bits (actual 32M bits) density is presented. The MLC ROM is designed by a 0.090 μm CMOS logic process. The ROM cell of 0.40μm ×0.50μm with 0.03μm per step of the channel width and channel length increase is determined to obtain 4 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 5 ns. 4 bits per cell can be achieved by inserting more referencing columns of ROM cells to track and to compensate noise from power and ground bouncing.

A Flexible, Field-programmable ROM Replacement

For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.

How to design secure SoCs Part IV: Runtime Integrity Protection

In previous articles, we gave an overview about secure SoC architectures (Part I), about the importance of key management (Part II) and secure boot (Part III) - the first line of defense. Part IV of the series focuses on runtime integrity protection, a paramount, ensuring the application remains secure even during active operation.

Frequently asked questions about ROM IP cores

What is VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits?

VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits is a ROM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this ROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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