Vendor: Analog Bits Inc. Category: PLL

Spread Spectrum PLL on TSMC CLN40LP-ULP

It isa requirement by FCC that allelectronic devices including game-consoles, PCs, and high speed compute servers, limit Electrom…

Overview

It isa requirement by FCC that allelectronic devices including game-consoles, PCs, and high speed compute servers, limit Electromagnetic Interference (EMI) when they distribute high-speed signals.

Analog Bits’ spread spectrum clock generation macro is capable of generating fine clock spreads that help reduce EMI. The precision spread-spectrum clock spreading is achieved by a combination of integer and fractional multiplication. The fractional divider generates a programmable triangular waveform to precisely control the degrees of spread. Programmable options allow the user to control the degree of spread in fine steps of +0/-0.5% and up to +0/-1.5% of the output clocks.

The spread spectrum macro is integrated with the PLL macro and is implemented in Analog Bits’ proprietary architecture. The combined spread-spectrum generation and PLL is the smallest PLL in the industry. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The spread spectrum generation PLL macro may be either IO pad ring or core integrated.

Silicon Proven Analog Bits’ spread spectrum architecture is in volume production in Xbox 360.

FNOM Frequency Spreading FNOM - % TMOD = 31.25 μs Figure 1: Precision Modulation Creating Spread Spectrum Clocks and Typical Layout of SSCG PLL

Key features

  • Electrically Programmable Macro for Spread Spectrum Clock Generation
  • Fractional divide control option allows fine spread control +0/-1.5% in steps of -0.5%
  • Module integrated in Analog Bits standard PLL/Frequency Synthesizer
  • Implemented with Analog Bits’ proprietary architecture using logic devices only
  • May be fully integrated inside customer specific IO ring or in the core
  • Smallest Spread spectrum PLL in the industry
  • Lowest power consumption – less than 4mA including the PLL
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection with or without spreading

Silicon Options

Foundry Node Process Maturity
TSMC 40nm LP

Specifications

Identity

Part Number
Spread Spectrum PLL on TSMC CLN40LP-ULP
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Spread Spectrum PLL on TSMC CLN40LP-ULP?

Spread Spectrum PLL on TSMC CLN40LP-ULP is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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