Vendor: Cadence Design Systems, Inc. Category: UART

Simulation VIP for UART

Best-in-class UART Verification IP for your IP, SoC and system-level design testing.

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs.

Cadence provides a mature and comprehensive Verification IP (VIP) for the UART protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for UART provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UART helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog along with the Universal Verification Methodology (UVM).

Supported Specification: Standard UART 16550 Specification

Key features

  • Mode
    • Synchronous, Asynchronous
  • Transmission Mode
    • Full-Duplex, Half-Duplex
  • Baud Rate
    • Configurable baud rate generation
  • Word Length
    • Configurable word length (5, 6, 7, or 8-bits)
  • Stop Bits
    • Configurable stop bits (1, 1.5, or 2-bits)
  • Error Detection Flags
    • Overrun, Frame, and Parity error
  • IDLE Frame Insertion/ Detection
    • Supports IDLE frame insertion and detection on transmitter and receiver respectively
  • TX/RX FIFOs
    • Supports up to 128-bytes FIFO depth for both transmitter and receiver
  • Auto Flow Control
    • Supports hardware flow control
  • Extended Features
    • LIN, MODBUS, Driver Enable, IRDA, Smartcard, and LPUART

Block Diagram

Simulation VIP for UART block diagram

Specifications

Identity

Part Number
Simulation VIP for UART
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about UART IP core

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

How to design secure SoCs, Part V: Data Protection and Encryption

In today’s connected world, where data is a crucial asset in SoCs, Part V of our series explores how to protect and encrypt data, whether at rest, in transit, or in use building on our earlier blog posts of the series: Essential security features for digital designers, key management, secure boot, and runtime integrity.

Not all overvoltage tolerant GPIOs are the same

Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.

Frequently asked questions about UART IP cores

What is Simulation VIP for UART?

Simulation VIP for UART is a UART IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP