Vendor: SmartDV Category: UART

USART Verification IP

USART Verification IP provides an smart way to verify the USART component of a SOC or a ASIC.

Verification IP View all specifications

Overview

USART Verification IP provides an smart way to verify the USART component of a SOC or a ASIC. The SmartDV's USART Verification IP is fully compliant with standard USART ds8251 Specification and provides the following features.

USART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

USART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Fully compatible with ds8251.
  • Transmit and receive commands allow the user to transmit and receive USART data.
  • Configurable Baud rate.
  • Programmable word length, stop bits, and parity
  • Offers divide-by-1, -16, or -64 mode
  • Supports synchronous and asynchronous operation
  • Uses approximately 528 FLEX logic elements (LEs)
  • Includes:
    • Error detection
    • False start bit detection
    • Automatic break detection
    • Internal and external sync character detection
  • Full duplex operation.
  • Fully configurable serial interface.
  • Data width from 5 bit to 8 bits.
  • Number of Stop bit configuration.
  • Parity type,
    • Even
    • Odd
    • No parity
  • Error Injection and detection for following,
  • Framing Error
  • Parity Error
  • FIFO depth is programmable
  • Monitor detects following,
    • Parity Errors
    • Framing Errors
  • Supports constraints Randomization
  • Callback in BFM and Monitor for wide range of events to help execute user code.
  • On-the-fly protocol and data checking
  • Ability to transmit strings to help verification of SOC.
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
  • USART Verification IP comes with complete testsuite to verify each and every feature of USART specification.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Status counters for various events in bus.
  • Built in functional coverage analysis.

Block Diagram

USART VIP block diagram

Benefits

  • Faster testbench development and more complete verification of USART designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the USART testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
USART VIP
Vendor
SmartDV
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about UART IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about UART IP cores

What is USART Verification IP?

USART Verification IP is a UART IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this UART?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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