Simulation VIP for SMBus

Incorporating the latest protocol updates, the Cadence^® Verification IP (VIP) for SMBus provides a complete bus functional model (BFM), integrated automatic protocol checks and coverage model. The VIP for SMBus is designed for easy integration in testbenches at IP, systems-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for SMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: SMBus v3.0

• SMBus Devices
  • Controller target, or host
• Packet Error Checking
  • Performs PEC on transmit and receive data on applicable packets
• Address Resolution Protocol
  • Resolve addresses for devices on the bus
• Device Timeout
  • Device timeout condition detection
• Bus Protocol
  • All bus protocols with and without a packet error code
• Alert Response Address
  • Alert response protocol for device controller capability
• Clock Generation and Data Arbitration
  • Clock generation using defined clock timings and data arbitration
• Clock Synchronization Between Two Controllers
  • Clock synchronization when more than one controller drives clock
• Optional SMBus Signals
  • SMBSUS in suspend-resume mode signal and SMBALERT for (interrupt line for target signal)