Vendor: Cadence Design Systems, Inc. Category: Soundwire

Simulation VIP for MIPI SoundWire

In production since 2015 on dozens of production designs.The Cadence®Verification IP (VIP) for the MIPI® SoundWiresm Protocol pro…

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Verification IP View all specifications

Overview

In production since 2015 on dozens of production designs.

The Cadence®Verification IP (VIP) for the MIPI® SoundWiresm Protocol provides a bus functional model (BFM), integrated automatic protocol checks and coverage model. It supports active or passive Manager, monitor, and a configurable number of Peripherals (1-11).

The VIP for SoundWire runs on Cadence <a href="/products/fv/enterprise_simulator/pages/default.aspx">Incisive® Enterprise Simulator</a>, as well as third-party simulators, and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Supported Specifications: MIPI SoundWire specifications v1.0, v1.1, and v1.2.

Key features

  • Multi-lane Payload Transport
    • Up to 8 data lanes are supported
  • High-PHY Mode
    • High-performance PHY
  • Synchronization
    • Sync Peripheral with Manager SoundWire frame
  • Enumeration
    • Manager assigns Dev_num for each newly attached Peripheral
  • Data Payload Traffic
    • Peripheral and Manager devices can send data payload traffic
  • Bank Switching
    • Frame size and DP channels can be switched during activity
  • Resets
    • Ability to perform all kinds of resets on the fly
  • Error Scenarios
    • Manager and Peripheral can generate error scenarios
  • Interrupts
    • Peripheral VIP replies automatically when interrupt needs to be generated based on configuration
  • Dynamic Peripheral Devices
    • Dynamic addition and removal of Peripheral devices
  • Multicast and Broadcast Peripheral Accesses
    • Manager can access Peripheral registers through broadcast and multicast
  • Test Data Modes
    • Support of static and PRBS data payload sending
  • Peripheral Command Responses
    • Peripheral VIP automatically replies with appropriate command responses
  • Command Ownership
    • Monitor can take command ownership from Manager
  • Flow Control
    • Peripheral and Manager devices can send asynchronous data payload traffic
  • Bulk Payload
    • Peripheral and Manager devices support Bulk Payload Transport Protocol
  • Manager PHY Test mMdes
    • Manager device supports PHY test modes
  • Full, reduced, and simplified data ports
    • Support in Full, Reduced, and Simplified Data Ports
  • Limited WordLength
    • Support in a limited set of values of the WordLength field
  • SDCA Interrupt Handling
    • Support all the SDCA interrupt registers and interrupt cascading
  • Severe Reset
    • Support to handle severe reset condition added
  • PHY Controlling Registers
    • Added support for PHY controlling registers

Block Diagram

Simulation VIP for MIPI SoundWire block diagram

Specifications

Identity

Part Number
Simulation VIP for MIPI SoundWire
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about Soundwire IP core

Building a high-performance, low-power audio/voice subsystem

With the growing popularity of applications such as mobile gaming and voice triggering, the audio/voice subsystem is playing a prominent role in many mobile system-on-chip (SoC) designs. The subsystem must be designed to meet dual demands: high-performance, high-resolution audio stream processing as well as always-on, low-power voice trigger and recognition. Customizable digital signal processing (DSP) and audio/voice subsystem solution intellectual property (IP) blocks can provide a cost-effective and efficient way to develop and deliver high-performance audio/voice products.

How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC

In the race to build smaller, smarter, and more efficient devices, audio system-on-chips (SoCs) must meet increasingly demanding requirements: high fidelity, low latency, low power, and seamless integration. The SoundWire PHY from Arasan Chip Systems is engineered to meet these challenges and elevate your next audio SoC design from standard to standout.

Frequently asked questions about SoundWire IP cores

What is Simulation VIP for MIPI SoundWire?

Simulation VIP for MIPI SoundWire is a Soundwire IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Soundwire?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Soundwire IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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