Simulation VIP for MIPI SoundWire-I3S

Best-in-class MIPI® SoundWire-I3Ssm (SWI3S) Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for SoundWire-I3S (SWI3S) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for SWI3S runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality. It supports Manager, and a configurable number of peripherals (1-8).

Supported Specifications: MIPI SoundWire-I3S specification version 0.4r36, October 2022

• PHYs
• Supports LC PHY and DLV PHY
• Interfaces
• Supports serial interface
• Resets
• Ability to perform power on reset and bus reset
• Peripheral Devices
• Multiple peripherals supported (up to 8)
• Command Transfer
• Manager and peripheral devices can perform ping, write, read command transfer only
• Clock and Data recovery
• Peripheral can lock to row syncs to generate CDR clock
• Strength Driving
• Manager and peripheral supports driving and identifying different driving strengths modeled as Verilog net strengths
• Glitch Filtering
• Manager and peripheral can filter glitches during Link control and Reset
• Phy Control Register
• Register to control PHY behavior (DoBusReset, StopLink, and Peripheral WakeUp, etc.)
• Error Injection
• Manager and peripheral support 8B-10B encoding errors and inserting glitches during bus reset
• Transport and Protocol errors
• Manager and peripheral can detect transport and protocol errors
• Codeword Endianness
• Supports Little and Big endian modes
• Link control sequences
• Supports bus reset, coldstandby-wake, and sleep-wake sequences