Vendor: Cadence Design Systems, Inc. Category: MIPI RFFE

Simulation VIP for MIPI RFFE

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® RF Front-End Control Interface (RFFEsm) protocol.

Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® RF Front-End Control Interface (RFFEsm) protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for RFFE provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for RFFE helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for the RFFE v1.0.0a, v1.10a, v2.0, v2.1, and v3.0.

Key features

  • Topology
    • Multiple subordinate and multiple main devices topology
  • Packet Generation
    • Command, Address, Data, and No Response Frame generation
    • Main device supports main write/read and also main context transfer write/read
    • Supports all RFFE commands
  • Device Address Types
    • Supports MID, GSID, USID, and BSID device addresses
  • Triggers
    • User-configurable triggers, timed triggers, external triggers and mTrig
  • Bus Park Cycle
    • Subordinate-initiated bus park, main-initiated bus park, and silent bus park cycle
  • SSC
    • Generation and detection of Sequence Start Condition (SSC)
  • Bus Ownership Transfer
    • Main ownership handover for multi-main topology
  • Modes
    • Normal mode and secondary mode
  • HSDR
    • Half-Speed Data Response for read access
  • Programmable USID
    • All three methods to program Unique Subordinate ID
  • Score Boarding
    • Compares read data with expected data based on none/any/many trigger(s) happening for that address
  • Error Injection
    • Inject and detect parity errors in any frame (command, address/data), various errors can be injected and detected as well in main ownership transfer command
    • Invalid command frame
    • Manipulate trigger supported register addresses from backdoor
  • Event Notification
    • Notification for command/address/data frames sent, timed trigger event occurred and reset occurred
  • Interrupt Capable Subordinate
    • Supports Interrupt Summary and Identification Command Sequence for RFFE v2.0 and RFFE v2.1

Block Diagram

Simulation VIP for MIPI RFFE block diagram

Specifications

Identity

Part Number
Simulation VIP for MIPI RFFE
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about MIPI RFFE IP cores

What is Simulation VIP for MIPI RFFE?

Simulation VIP for MIPI RFFE is a MIPI RFFE IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI RFFE?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI RFFE IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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