Vendor: SmartDV Category: MIPI RFFE

MIPI RFFE PSVIP

MIPI RFFE Post Silicon Validation IP provides a smart way to post silicon validation of the MIPI RFFE component of a SOC.

Verification IP View all specifications

Overview

MIPI RFFE Post Silicon Validation IP provides a smart way to post silicon validation of the MIPI RFFE component of a SOC. MIPI RFFE Post Silicon Validation IP provides an smart way to post silicon validation of the MIPI RFFE bi-directional two-wire bus. The SmartDV's MIPI RFFE Post Silicon Validation IP is fully compliant with version 1.0,2.0,2.1 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.

MIPI RFFE PSVIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI RFFE PSVIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports 1.0,2.0 and 2.1 MIPI RFFE Specification.
  • Supports Full MIPI RFFE Master and Slave functionality.
  • Operates as a Master, Slave, or both.
  • Supports all topologies as per the MIPI RFFE specification.
  • Supports multiple slaves.
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
    • Bus ownership transfer
    • Interrupt polling
    • Master write and read
    • Master context write and context read
  • Supports various kind of Master and Slave errors generation
    • Undefined command frame
    • Command frame with parity error
    • Command frame legth error
    • Address frame with parity error
    • Data frame with parity error
    • Read of unused register
    • Write of an unused register
    • Read using the broadcast ID or a GSID
    • Various errors in Bus ownership transfer
  • Supports extended register read/writes.
  • Supports interrupt summary and identification command sequence.
  • Supports Master ownership handover.
  • Support Master write and read sequence.
  • Supports device enumeration.
  • Supports low power testing.
  • Supports bus-accurate timing.
  • Supports programmable speed.

Block Diagram

MIPI RFFE PSVIP block diagram

Benefits

  • Runs in custom FPGA platforms
  • Validate RFFE device for compliance

What’s Included?

  • Linux Perl Driver to control the PSVIP
  • Encrypted RTL of PSVIP or Bit file for selected FPGA platform
  • Complete regression suite containing all the MIPI RFFE testcases
  • Detailed documentation of all functions of perl driver and testcases
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
MIPI RFFE PSVIP
Vendor
SmartDV
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about MIPI RFFE IP core

The Complicated Chip Design Verification Landscape

While a working device that meets all functional specifications is a chip design project group’s No. 1 goal, many designers wake up covered in sweat worrying about a dead-on-arrival chip. No matter how much coverage or how many verification tools are employed, a bug or multiple bugs could slip through the net.

RISC-V's CPU Verification Challenge

RISC-V is new and does not have the benefit yet of years of field-proven experience. This means that a carefully chosen and executed CPU verification strategy is essential. It also means that the availability of a “golden reference model” is a critical component that must be secured.

Frequently asked questions about MIPI RFFE IP cores

What is MIPI RFFE PSVIP?

MIPI RFFE PSVIP is a MIPI RFFE IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this MIPI RFFE?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI RFFE IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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