HBM IP Listing

A 0.9V/1.2V I/O Library in TSMC 55LP.

• TSMC
• 55nm
• GP

The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …

• GPIO
• Pre-Silicon
• Available Now

Synopsys HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.

• Controller

The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base …

• TSMC
• 28nm
• HPC+
• In Production

The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps…

• Controller + PHY + 1
• DDR3 + 1
• UMC
• 28nm
• HPC
• In Production

This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput.

• Controller + PHY + 1
• DDR3 + 1
• TSMC
• 28nm
• HPC+
• In Production

The W65C816i1M16SA Microcontrollers have interfaces for connected Things for sensing, processing, communicating and actuating (SP…

• MCU
• RTL Soft Core - 2+ years
• FPGA specific deliverables available now; Can be converted to ASIC

The W65Cx65 Microcontrollers have interfaces for connected Things for sensing, processing, communicating and actuating (SPCA).

• MCU
• RTL Soft Core - 2+ years
• FPGA specific deliverables available now; Can be converted to ASIC

The SMBus library provides open-drain bi-directional I/O cells designed for the High-Power SMBus two-line interface.

• TSMC
• 7nm
• N7+
• Silicon Proven

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.

• TSMC
• 7nm
• N7+
• Silicon Proven

The 3.3V Support: Power library provides a full complement of cells to support the assembly of a pad ring by abutment.

• TSMC
• 7nm
• N7+
• Silicon Proven

A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with associated ESD cells.

• TSMC
• 180nm
• BCDG2

The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage ref…

• TSMC
• 7nm
• N7+
• Silicon Proven

The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers ope…

• TSMC
• 7nm
• N7+
• Silicon Proven

The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …

• SMIC
• 40nm
• Silicon Proven

HBM3 Memory Model provides an smart way to verify the HBM3 component of a SOC or a ASIC.

• Controller

HBM2E Memory Model provides an smart way to verify the HBM2E component of a SOC or a ASIC.

• Controller

HBM3 DFI Verification IP provides an smart way to verify the HBM3 DFI component of a SOC or a ASIC.

• Verification IP
• Controller

HBM2E DFI Verification IP provides an smart way to verify the HBM2E DFI component of a SOC or a ASIC.

• Verification IP
• Controller

HBM3 Synthesizable Transactor provides a smart way to verify the HBM3 component of a SOC or a ASIC in Emulator or FPGA platform.

• Controller