Vendor: Aragio Solutions Category: GPIO

I2C IO Pad Set

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.

Contact Provider Request Datasheet
TSMC 7nm N7+ Silicon Proven View all specifications

Overview

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface. It is compliant with the I2C-bus specification – UMC10204 I2C-bus specification and user manual, Rev.4 – 13 February 2012, NXP.
The design supports the Sm, Fm and Fm+ modes of operation at the I2C bus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
This 7nm library is available in a staggered flip chip implementation.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the I2C cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)

Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C

What’s Included?

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7+ Silicon Proven

Specifications

Identity

Part Number
RGO_TSMC07_18V33_7FF_20C_I2C
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Contact Aragio Solutions

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Frequently asked questions about GPIO Pad Library IP cores

What is I2C IO Pad Set?

I2C IO Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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