I2C IO Pad Set

The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface. It is compliant with the I2C-bus specification – UMC10204 I2C-bus specification and user manual, Rev.4 – 13 February 2012, NXP.
The design supports the Sm, Fm and Fm+ modes of operation at the I2C bus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
This 7nm library is available in a staggered flip chip implementation.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the I2C cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)

Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C

• a. Physical abstract in LEF format (.lef)
• b. Timing models in Synopsys Liberty formats (.lib and .db)
• c. Calibre compatible LVS netlist in CDL format (.cdl)
• d. GDSII stream (.gds)
• e. Behavioral Verilog (.v)
• f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
• g. Databook (.pdf)
• h. Library User Guide - ESD Guidelines (.pdf)