HBM IP Listing

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3E

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3E

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.

• TSMC
• 40nm
• G

The Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules.

• Single-Protocol PHY

The JESD204B Tx-Rx PHY IP interface, which offers total support for the JESD204B synchronous and serial data interface, is aligne…

• SMIC
• 40nm
• LL
• In Production

The JESD204B Tx-Rx PHY IP interface, which offers full support for the JESD204B synchronous and serial data interface, is aligned…

• Single-Protocol PHY
• In Production
• Immediate

With the JESD204B Tx-Rx PHY IP interface, which fully supports the JESD204B synchronous serial interface, the JESD204B version sp…

• Single-Protocol PHY
• In Production
• Immediate

The JESD204B.01 version specification is compatible with the JESD204B Tx-Rx PHY IP interface, which offers support for the JESD20…

• UMC
• 28nm
• HPC
• In Production

In addition providing support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is consistent wi…

• SMIC
• 14nm
• SF+
• In Production

In order to provide full support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is compliant …

• Single-Protocol PHY
• In Production
• Immediate

Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via…

• TSMC
• 55nm
• LP
• In Production

The JESD204B Tx-Rx PHY IP Core, compliant with the JESD204B.01 version specification offers support for the JESD204B synchronous …

• TSMC
• 28nm
• HPC+
• In Production

The RF libraries include analog signal pads and ESD protection components for RF applications.

• High-Speed
• Pre-Silicon
• Available Now
• RF

eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.

• TSMC
• 22nm
• ULP
• In Production

The 1.2V GPIO library provides a bidirectional I/O driver for Parallel Trace Interface applications.

• GPIO
• Pre-Silicon
• Available

HBM3 Memory Controller

• Controller

The AT32X22B180GN0AA is organized as a 32 by 22 one-time programmable (OTP).

• X-FAB
• 180nm
• XH018
• Available on request

HBM2E Memory Controller

• Controller

HBM2 Memory Controller

• Controller

The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.

• Single-Protocol PHY