What is HBM2 Memory Controller?
HBM2 Memory Controller is a HBM IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub.
Vendor:
Global UniChip Corp. (GUC)
Category:
HBM
HBM2 Memory Controller
HBM2 Memory Controller
Overview
HBM2 Memory Controller
Key features
- Support Pseudo Channel mode with 64DQ per Pseudo Channel
- Support DFI1:1
- Support HBM Burst Length 4
- Support 4 High or 8 High HBM Devices
- Support only 1 AXI 4.0 ports with 128-bit data bus width for each Pseudo channel
- Support only AXI burst type = INCR, AXI burst length = 8, AWSize/ARSIze = 3’h4 (128-bit), and AWAddr/ARAddr is 128-Byte aligned
- Support only Parity Latency = 0 or 2
- Support Read DBI and Write DBI features
- Support Command/Address parity check feature
- Support DQ parity check feature
- Support both mode-1 and mode-2 DWORD remapping features
- Support HBM ECC function
- Support internal SRAM ECC function
- Support AXI read interleaving
- Consistent AXI read-after-write
- Support software programmable mapping from AXI address to SID, Bank-Group, Bank, Row, Column bits for user specific applications
- Support manual self-refresh and automatic self-refresh
- Support manual power-down and automatic power-down
- Support single bank refresh
- Support auto precharge
- Support memory BIST (Built In Self Test) function
Specifications
Identity
Part Number
IGDHBM002A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
Frequently asked questions about HBM Interface IP
How should engineers evaluate this HBM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.