Syntacore
•
HQ:
Cyprus
SCR5 is an efficient, silicon-proven, entry-level Linux-capable 32/64-bit RISC-V processor core.
- MCU
Compare 274 RISC-V IP Listing from 63 vendors
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Syntacore• HQ: Cyprus
SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionalit…
- MCU
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Syntacore• HQ: Cyprus
SCR3 is an efficient, silicon-proven, microcontroller-class, 32/64-bit RISC-V processor core.
- MCU
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Syntacore• HQ: Cyprus
SCR1 is an open-source and silicon-proven RISC-V-compatible, 32-bit, entry-level, MCU-class core.
- MCU
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I3C Controller IP- Slave, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- MIPI Alliance – Specificati…
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I3C Controller IP – Master, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- MIPI Alliance – Specificati…
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I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
Digital Blocks, Inc.• HQ: USAThe DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
- I2C / I3C
- Successful in Customer Implementations
- Immediately
- MIPI Alliance – Specificati…
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Roa Logic BV• HQ: The Netherlands
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as sp…
- Timers & Watchdogs
- Source Code Available Immediately
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CAST• HQ: USA
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master int…
- Bus Fabric
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Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
Digital Blocks, Inc.• HQ: USAThe DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Inte…
- Display Controller
- Successful in Company FPGA Kit Demo Reference Design, Customer Products
- Immediately
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Display Controller - LCD / OLED Panels (AXI4 Bus)
Digital Blocks, Inc.• HQ: USAThe DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protoc…
- Display Controller
- Successful in Company FPGA Kit Demo Reference Design, Customer Products
- Immediately
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Display Controller - LCD / OLED Panels (AXI Bus)
Digital Blocks, Inc.• HQ: USAThe DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconn…
- Display Controller
- Successful in Company FPGA Kit Demo Reference Design, Customer Products
- Immediately
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Vtool Ltd.• HQ: Israel
RISC-V-based customizable SoC
- RISC-V
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ML-KEM Key Encapsulation IP Core
CAST• HQ: USAThe KiviPQC™-KEM is a hardware accelerator for post-quantum cryptographic operations.
- CRYSTALS-Kyber (ML-KEM)